1. Field of the Invention
The present invention relates generally to a pulsewidth control loop (PWCL) device with complementary signals, and more particularly, to a PWCL with operation stability-increasing, process variation-reducing and power dissipation-saving functions.
2. Description of the Prior Art
In some complementary metal-oxide semiconductor (CMOS) RF power amplifier designs, the output power is most efficiently consumed at a 50% pulsewidth. The buffer and delay elements are inserted between the source and destination of signals to adjust the pulsewidth. The buffer and delay elements are composed of some delay elements. The pulsewidth of a clock signal is determined by a phase-locked loop (PLL). The oscillator of a PLL operates at twice the required frequency. Then the operating frequency is divided by two, and yields a 50% pulsewidth. Multiplying up the oscillator frequency results in more power dissipation. Furthermore, this approach is in prejudice of designing oscillators for a wide-range operating frequency.
The digital PWCL at present is proposed to overcome the shortcomings of the conventional PLL. It has high ability of immunity to noise and a short locking time. The PWCLs are applied in system-on-chip (SOC) designs, delay locked loops (DLL) and phase-locked loops (PLL) to adjust the pulsewidth of a clock signal. As the demand on operation frequency of SOC increases, the variation of the pulsewidth is indeed a bottleneck in designing, and for low-voltage design aspects, reducing the supply voltage of a circuit is also inevitable.
Referring to FIG. 1, it schematically shows a PWCL circuit of system-on-chip device 100. The PWCL circuit includes a control stage circuit 110, a buffer chain 120, an oscillator 130, two charge pumps 140 and 150, one comparator 160, and three bypass capacitances C1˜C3. The control stage circuit 110 is used to receive a clock signal Ckin and a control signal Vctr from the feedback of the comparator 160. Then it outputs a signal to the buffer chain 120, and generates an output signal Ckout from the buffer chain 120 to the charge pump 140. And then it outputs another signal from the oscillator 130 to the charge pump 150. Then, the charge pumps 140 and 150 output Vc and Vref to the two inputs of the comparator 160 individually. It will generate a control signal Vctr and feedback the control signal Vctr to the control stage circuit 110. Besides, one end of the bypass capacitance C1 is coupled with the output of the charge pump 140 and the positive input of comparator 160, and the other end is grounded. One end of the bypass capacitance C2 is coupled with the output of the charge pump 150 and the negative input of the comparator 160, and the other end is grounded. One end of the bypass capacitance C3 is coupled with the output of the comparator 160, and the other end is grounded. When the pulsewidth of Ckout is under 50%, there is longer time for the charge pump 140 to charge C1 and Vc increases. Therefore, control signal Vctr of the comparator 160 rises, increasing the pulsewidth of Ckout. Finally, Vc equals Vref when the PWCL device 100 is stabilized. Ckout reaches a 50% pulsewidth. When the pulsewidth of Ckout exceeds 50%, the charge pump 140 discharges more current and makes Vc fall. Control signal Vctr of the comparator 160 falls, reducing the pulsewidth of Ckout. Then, Vc equals to Vref when PWCL device 100 is stabilized. Finally, Ckout reaches a 50% pulsewidth.
The oscillating frequency of the oscillator 130 is constant, and is unrelated to the clock signal Ckin. Input signals from the charge pumps 140 and 150 are two individual signal sources (because the frequency and the phase of two signal sources are unrelated). Therefore, the voltage error (Vc−Vref) of the control loop device increases, leading to a possibly unstable operation. On the other hand, the process variation of the buffer chains 120 and oscillator 130 reduces the accuracy of the pulsewidth.